1. Field of Invention
The invention is related to methods and apparatus for semiconductor fabrication, and, more particularly, to methods and apparatus for deposition of films on patterned substrates.
2. Discussion of Related Art
For many decades, dry processing techniques, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have played a dominant role in integrated circuit (IC) metallization processes. Today, electroplating via wet chemistry methods can be an effective alternative to PVD and CVD methods for some applications. Metallization processes that utilize electroplating, however, still typically require a preliminary PVD step to provide a seed layer, a diffusion barrier and/or an adhesion layer (e.g., a layer of Ti, Ta, TiN, or TaN.)
During microelectronic device fabrication, films are often deposited on non-planar surfaces. The formation of electrical interconnect, for example, can entail the deposition of thin films of metals on patterned substrates. The completed interconnect provides electrical connections between components, such as transistors, in an IC, and between the IC and a package.
The complex interconnections between transistors in modern ICs require the use of several layers of metal wiring that are embedded in interlayer dielectric (ILD) materials. The metal lines at each layer can be formed by filling “trenches” patterned into the ILD. In addition, connections between metal lines of different layers are made by metal-filled holes, i.e., vias. Vias from a first metal layer to a transistor are also referred to as contacts.
The surface topography that wafers exhibit at various steps in a fabrication process arise from patterned features related to, for example, the trenches and/or vias described above. Film deposition through PVD on such wafers can, unfortunately, suffer from shadowing effects. Shadowing effects can cause, for example, poor step coverage on sidewalls and bottoms of trenches and vias, and can cause overhanging structures to form at the top corners of the trenches and vias. These effects can lead to void formation when attempting to fill a surface feature.
Problems related to poor step coverage and void formation are exacerbated as circuit dimensions shrink and aspect ratios of features increase. Due to geometrical shadowing, a film can preferentially deposit near the top corners of a trench or via, and the coverage is poor especially at the bottom corners. Overhangs can cause additional shadowing of sidewalls and bottoms, exacerbating the problem of void formation. The angular distribution of a typical incident flux further complicates control of step coverage.
Directional PVD (DPVD) and ionized PVD (IPVD) techniques can be used to mitigate the step-coverage problems associated with PVD. Common DPVD techniques include long-throw deposition and collimated sputter deposition. Long-throw deposition entails an increased target-to-substrate separation, while collimated sputter deposition uses a collimator cell disposed between a target and a substrate to filter obliquely incident material. Thus, a flux can be made more normal to a wafer by reducing flux divergence, and a greater portion of incident atoms can reach bottoms of features. DPVD, however, typically suffers from poor efficiency, high cost, and can still exhibit poor sidewall coverage and void formation.
In IPVD, atoms approaching a substrate pass through a high-density plasma discharge, and a substantial portion become ionized. A negative bias applied to the substrate attracts the ionized flux of atoms, increasing their directionality and energy in comparison to traditional PVD. When the energies of these ions are set to high enough values, they can re-sputter the overhangs to improve conformality.
Re-sputtered atoms from the bottom of a trench or via can deposit on a nearby sidewall to further improve step coverage. The effectiveness of IPVD, however, is sensitive to atomic ionization rates and to the aspect ratio (AR) values of the patterned surface topography. Excessive re-sputtering often causes the formation of bevels on top corners, and can expose underlying dielectric material. Moreover, re-sputtered material can deposit on the higher parts of sidewalls and thus lead to formation of overhangs and voids.